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 June 25th, 2006 | #1 (permalink) | ||||||||
| Senior Member   justzikle has no status.
Location: At My Place Rep Power: 6  Gender:  Country:    |  Is it correct?? Hi all System is option 61c RLS 4. Now i have connected two clock controllers card in CPU0 and CPU1 (both in slot 9) with Dual DDP2 PRI card as follows. DDP2 card in CPU0, loop 2 and 3 CLK0----------------->J1 Secondary (CC in CPU0) PORT0 CLK1----------------->J1 Secondary (CC in CPU1) -------------------------------------------------------------- DDP2 Card in CPU1 , Loop 18 and 19 CLK0--------------------> J2 Primary (CC in CPU0) PORT0 CLK1-------------------> J2 Primary (CC in CPU1) are thes connections OK?? How do i track it to primary clock??? I mean how do i defined primary and secondary Clock in LD73(SYTI data)??? Any help in this matter? I read NTP`s but didnt understand.. Regards | ||||||||
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| June 26th, 2006 | #5 (permalink) | ||||||||
| Junior Member
Rep Power: 5 | An Option 61C has 2 clock cards and only 2 referance loops. Your cabling is correct if you make loop 18 the primary referance and loop 2 the secondary referance. Program LD 73 as follows: PREF 18 SREF 2 It helps to visualize you are receiving the primary clock source from the CO on Loop 18 and extending the cables to the J2 ports on the clocks. You are receiving the secondary clock source from the CO on Loop 2 and extending the cables to the J1 ports on the clocks. Check the clock status in LD 60. SSCK 0 SSCK 1 | ||||||||
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